This invention relates to reducing static and total power in electronic devices. More particularly, this invention relates to reducing static and total power consumption in a programmable logic device (PLD)1. 1 The term PLD as used in this patent is intended to cover the broad space of programmable logic. This includes devices commonly known as CPLDs (Complex Programmable Logic Devices) such as MAX 7000 from Altera Corp. of San Jose Calif., FPGAs (Field Programmable Gate Arrays) such as Stratix from Altera, or Structured ASICs (metal programmable logic) such as Hardcopy from Altera.
Gate thickness of transistors in PLDs have always trended thinner and thinner. As the gate thicknesses approach 90 nanometers, the transistors do not fully turn OFF. Thus, a pass gate in the OFF position continues to pass some current. It follows that the source of power consumption in the static state of such a PLD having thin gate thicknesses tends to come from the leakage of any transistor in the PLD because the power required maintain transistor states increases.
There is also an additional gate leakage effect that exists at 90 nm gate thickness but which becomes very large at 65 nm—(and smaller) gate thickness. This additional gate leakage effect may be either gate to substrate leakage or gate to source/drain leakage.
PLDs are typically designed with a multitude of field-effect transistors (FETs). When a FET is turned OFF, the leakage depends for the most part on whether there is a voltage difference between the source and the drain. The majority of power consumption in the static state of a PLD which implements 90 nanometer line widths comes from leakage of FETs. The leakage of the FETs results from a voltage differential existing between the drain and the source combined with the transistor not fully turning itself OFF.
Therefore, it would be desirable to optimize a PLD to consume less power, even at relatively narrow gate widths, while maintaining the level of the functionality of the PLD.